Minutes of the IFIP Working Group Meeting

Montpellier, LIRMM, December 5th, 2001

Present: F.Wagner, F.Rammig,M.Glesner, M.Robert, R.Reis, D.Borrione, L.Claesen

Invited: L.Pierre

Apologies: J.Damore, J.Darringer, A.Jerraya, D.Sciutto, P.Ivey, J.Mermet,R.Waxman, R.Camposano, G.Milne, N.Fristacky, N.Dutt,P.Paulin, W.Grass, K.Müller-Glaeser, S.Johnson,D.Gale, O.Koufopavlou, C.Delgado Kloos, K.-H.Diener, A.Pawlak, R.Hartenstein

 

1. VLSI'2003

The proposal for organizing the next edition of theVLSI conference in Darmstadt, Germany, in 2003, has been approved. Generalchair will be Prof. Manfred Glesner.

It has been decided that a Steering Committee for theVLSI conference series will bre created. This committee will be composedby Manfred Glesner, by the general chairs of the 3 former editions ofthe conference (Ricardo Reis, Luis Miguel Silveira and Michel Robert)and by two additional WG members, still to be appointed, one from NorthAmerica and one from Asia.

Although the conference shall cover all topics of interest of WG 10.5, it must have an emphasis on a main subject. Systems-on-chip,already taken as main subject in the Montpellier edition, may be retained.

The strategy of editing conference proceeedings withall selected papers and a further book only with the best papers, selected after the conference by the programme committee, already adopted thisyear, will be maintained for the next edition.

The Steering Committee will bring a concrete projectof the 2003 edition to the next WG meeting.

2. VLSI'2001

Michel Robert presented a report on the 2001 editionof the VLSI-SoC conference. The conference had more than 120 attendees.Three keynote speakers gave invited talks on relevant topics. 70 papershave been selected for presentation. The best conference papers, to beselected by the Programme Committee, will be included in a book to bepublished by Kluwer. Income and expenditures of the conference were around50 KEuros. This already includes the cost of the book.

The WG congratulated M.Robert and his team at LIRMMfor the excellent organization of VLSI-SoC'2001.


3. Report on SIG-CHARME

Laurence Pierre, from the University of Marseille,was appointed by SIG-CHARME to act as liaison to the WG and to presenta report at this meeting. SIG-CHARME is being created by a group of 26researchers. This report can be found at the end of these minutes.

Steve Johnson, who is also a WG 10.5 member, has beennominated as chair of SIG-CHARME.

Statutes and bylaws of SIG-CARME are being submittedto WG 10.5 for analysis and approval.

The main goal of SIG-CARME is to organize the CHARMEconference series, from which IFIP WG 10.5 is the only permanent sponsoringsociety. The SIG will also maintain a strong coordination with the organizationof the FMCAD conference series. CHARME and FMCAD will be always organizedin alternate years.

It has been decided that the creation of SIG-CHARMEwill be electronically submitted to the WG members for analysis. The finaldecision will be formally confirmed at the next meeting. It is hoped thatthe new SIG will be formally approved by TC10 and the IFIP General Assemblyat their next meetings in Montreal, during the IFIP World Congress.

4. Report on SIG-ES (Embedded Systems)

Franz Rammig has been appointed by Bernd Kleinjohann,SIG-ES chair, to present a report on the SIG. SIG-ES has currently around30 members, from which only around 10 are senior members. This is explainedby the fact that most members originate from the attendees of the DIPESworkshop, held in October 2000, during which the founding meeting of SIG-EStook place. The SIG will formally belong to WG 10.5, although it has beendecided that it will be also informally attached to WG 10.3 and WG 10.4.A formal proposal for the creation of SIG-ES shall be approved at thenext DIPES workshop, to be held in Montreal in August 2002, and then submittedto WG 10.5.

5. Report on SIG-DL (Design Languages)

Flavio Wagner briefly reported on the intention ofJohn Willis and Guido Schumacher (University of Oldenburg) to relaunchSIG-VHDL as SIG-DL (Design Languages). It has been decided that the WGwill vote on the discontinuation of SIG-VHDL or on the creation of a newSIG-DL at the next meeting. For that, a concrete proposal for the creationof the new SIG will need to be available.

6. Membership

The WG approved the following general criteria foradmission of new members, proposed at the last meeting in Pirenopolis:

  1. when the WG needs to expand its expertise to relevant or new subjects that are poorly covered by the current membership;
  2. when the WG needs to expand its membership in certain geographical regions; and
  3. to replace members that are leaving the group,when our coverage of a certain subject or region must be maintained.

Many members are not reacting to messages. As an exemple, 24 members did not answer the survey on research interests. It has beendecided that these members shall be contacted directly, if necessary bya printed letter, in order to know if they still have interest in beinga member of the WG. In case of a positive answer, they should expresshow they intend to contribute to the WG.

7. Aims and scope

The text defining the Aims of the WG shall beupdated. References to systems-on-chip and to embedded systems and softwareshall be included.

The Scope of the WG must be proposed, discussedand approved. Suggestions may be taken from the scope of the SIGs. TheScope shall consist of a few and broad topics.

F.Wagner presented the result of the survey on theresearch interests of the WG members. 40 members answered the survey.This results are attached to these minutes as an Appendix. The Scope ofthe WG shall reflect the emphasis of the members' interests.

8. Roadmap

The organization of an IFIP roadmap on design technologies, already proposed at the previous meeting, was discussed. A first versionof this roadmap should be defined at the WG meeting to be held in Montreal in August 2002.

A task force shall be created to lead this effort.It must define requirements and procedures for the elaboration of theroadmap and also negotiate support from ITEA and/or other organizations/ similar efforts, such as MEDEA and ITRS. Names for this task force havebeen suggested and will be contacted by the WG chair.

Franz Rammig volunteered to act as a liaison to ITEA.

It has been decided that the next WG meeting, to beheld on the occasion of DATE, shall be used to start the discussion onthe roadmap. For that purpose, the WG shall invite two speakers: J.Borel,who can present the MEDEA roadmap, and Raul Camposano, who may talk onthe challenges for the design of systems-on-chip. Their talks should givethe initial motivation and basis for a technical discussion to be heldduring the same meeting.

9. PhD forum

It has been proposed that an international PhD forumcould be held together with VLSI'2003 in Darmstadt. This forum would servefor the interchange of ideas and experiences of PhD students from differentparts of the world.

Funds may be obtained from IFIP and from other sourcesto support the participation of students. A committee would decide onthe allocation of these funds to candidate students, based on criteriastill to be established. It is known, for instance, that TC10 has an annualbudget and that WG 10.5 may compete for these funds, and that IFIP hasspecial funds for supporting activities that are related to developingcountries. Local support from Darmstadt for receiving the students willalso be seeked.

The Steering Committee of the VLSI conference willnominate a responsible for the PhD forum, in agreement with the organizingcommittee of VLSI'2003.

10. Next meetings

The next meeting will be held in Paris, on the occasion of the DATE conference on March. This meeting will comprise invited talksand a technical discussion, regarding a roadmap on design technologies.

The following meeting will be held in Montreal, onthe occasion of the IFIP World Congress and of the DIPES workshop, whichis sponsored by WG 10.5. This meeting will continue the discussion ofa roadmap on design technologies.




APPENDIX 1. REPORT ON SIG-CHARME

The people involved in the creation of SIG-CHARME already met and discussed the definition of its "Statutes and Bylaws":

- in November 2000 (during the FMCAD Conf., in Austin, TX)

- in September 2001 (during the CHARME Conf., in Edinburgh, UK)

A group of active researchers in the area of "FormalDesign and Verification Methods for Correct Hardware-like Systems" alreadyexists, the series of CHARME Conferences (or their ancestors) dates backto the end of the eighties. All these conferences have been supportedby IFIP WG 10.5 (or formerly 10.2). SIG-CHARME should bring this communityand its activities into a more concrete existence.

Currently,

- the statutes are ready to be submitted, Steve Johnson has been elected as SIG-CHARME Chair for a period of two years, andTom Melham has been elected SIG-CHARME Treasurer for the same period.

- there is a mailing-list (and the beginning of aWeb site)

- The 26 individuals on the "sig-charme" mailing list comprise the current membership of SIG-CHARME. An initiative to forma larger charter membership is now underway.

The current members are:

Alan Hu, University of British Columbia

Alan Mycroft, Cambridge

Andrew Martin, Motorola, Inc.

Byron Cook, Prover Technologies

Dominique Borrione, Laboratoire TIMA

Hans Eveking, TU Darmstadt

Ganesh Gopalakrishnan, University of Utah

Danny Geist, IBM/Haifa

Beneditto Intrigila, Universita` di L'Aquila

John O'Leary, Intel Corp.

Kanna Shimizu, Stanford

Ken Turner, University of Stirling

Laurence Pierre, Universite' do Provence

Luc Claesen, Smartpen, Inc

Mark Aagaard, Univ. Waterloo

Ken McMillan, Cadence, Corp.

Mary Sheeran, Chalmers Tekniska Hoegskola

Nicolas Halbwachs, Verimag

Sagi Katz, Galileo Co

Steven D. Johnson, Indiana University

Tom Melham, University of Glasgow

Thomas Kropf, Bosch, DE

Tiziana Margaria, Univ. of Dortmund

Enrico Tronci, Universita` di L'Aquila

Warren Hunt, IBM/Austin

Yossi Malkal, IBM/Haifa

The main aims of the SIG are:

- to organize SIG-CHARME meetings,

- to steer the CHARME series of Conferences (and toset up a financial machinery for running these conferences), and tocoordinate with FMCAD,

- to get more people involved in its activities,

- to promote education in formal methods

- to advance formal methods practive in systems applications



APPENDIX 2. RESULT OF THE SURVEY ON RESEARCH INTERESTS

Notes:

Design Methodology, Circuit and System Design

N1

N2

N3

System Design Methods

18

19

37

Architecture and Design of Embedded Systems

14

22

36

Platform Design and VC Reuse Methods

16

9

25

Embedded Software - RTOS, Compilation, Optimization

6

16

22

Reconfigurable Computing

14

8

22

Microsystems

14

3

17

Telecommunication Circuits and Applications

14

1

15

Design of Low Power Systems

8

6

14

Asynchronous Circuits

11

1

12

Analogue and Mixed-Signal Systems

7

2

9

Digital Signal Processing and Image Processing ICDesign

8

1

9

Autonomous Control

0

1

1

Memory Design for SoC

0

1

1

CAD Languages, Environments, Algorithms and Tools

N1

N2

N3

System Level Specification and Design Languages

17

18

35

Hardware/Software Codesign

16

15

31

Architectural Level Synthesis

22

7

29

Intellectual Property, Design Reuse, and Design Libraries

18

5

23

Formal Verification

14

6

20

Power Estimation

12

6

18

Emulation and Prototyping

12

6

18

Distributed, Networked, and Collaborative Design

8

8

16

Fundamental CAD Algorithms

14

2

16

Logic and Finite State Machine Synthesis

14

2

16

Management of DA Systems, Frameworks, and IntertoolCommunication

10

4

14

Design-for-Testability

11

1

12

Physical Design and Verification

6

4

10

Static Timing Analysis and Timing Verification

8

2

10

Discrete Simulation

5

4

9

Test Generation

6

3

9

Interconnect Modelling and CAD for Analogue and MixedSignal Design

4

4

8

Symbolic Techniques

5

3

8

Fault Modeling and Simulation

7

1

8

BIST

7

1

8

Electrical-level Circuit and Timing Simulation

0

7

7

EMC on Chip and High Density Packaging Level

6

0

6

Defect-Oriented Test and Failure Analysis

6

0

6

Analogue and Mixed-Signal Test

4

1

5

Test Resource Partitioning and System Test

5

0

5

Performance Analysis

0

2

2

Field-Oriented Test, On-line Testing and Dependability

2

0

2

SoC Debug

0

1

1

Component and platform software leverage for fastertime-to-market

0

1

1

Network processor, DSP and other standard parts leverage

0

1

1

to enable faster, more flexible R&D without ASCs

Physical Synthesis

0

1

1

Multi-processor design automation (embedded S/W tools,partitioning, RTOS)

0

1

1

Complex system-on-chip interconnect

0

1

1

System Test

0

1

1