IFIP Working Group 10.5
Minutes Meeting
Verona, October 7th (17:30-19:30)
In conjunction with VLSI-SoC 2018
Masahiro Fujita with the help of Prof. Dominique
Borrione and Prof. Salvador Mir
Attendees: Dominique Borrione, Salvador Mir, Fatih Ugurdag, Srinivas
Katkoori, Manfred Glesner, Ricardo Reis, Donatella Sciuto, Manfred Glesne, Carlos
Silva Cardena, Masahiro Fujita
Apologies: Giovanni De Micheli, Reiner Hartenstein, Chi Ying TSUI, Michael.Huebner,
Coskun, Ayse Kivilcim, Juergen Becker, Ian O'Connor, Luc Claesen, Eugenio Villar,
Kiyoung Choi
Agenda
Welcome and approval of
minutes of previous meeting
Introduction of the new member : Prof. Maciej Ogorzalek approved by mail
Status of VLSI-SoC 2018
Status of VLSI-SoC 2018
Discussion and decision
on VLSI-SOC 2021
Discussion on VLSI-SOC
2022
New member
Prof. Maciej Ogorzalek has been approved by email voting.
Welcome to
WG10.5
Review of VLSI-SOC 2018
Reported by
Graziano Pravadelli and the details can be seen in the slides at IFIP WG10.5
web.
94
registered
Acceptance
rate 27%
1/3
of submitted papers came from suggested TPC members, 9% came from non-suggested
TPC members, 56% came from people outside TPC.
2
papers were withdrawn because accepted as posters rather than oral
presentation.
Problems
with visa: India, China (some started asking too late). Acceptance letter
should warn to start paper work early. They need original official acceptance
letter.
Budget:
break-even was 90/100. So basically OK.
PhD
School co-located: Friday to Sunday. 17 participants: 16 from Italy, 1 from
Germany. 5 courses, 25 hours, 6 credits ECTS. Problem is the date. Teaching
class starts in October. Also there is a competing PhD school in July in Lipari.
There
are following discussions:
Ranking
of the conference has an influence on submission. In France: B. In Brazil: they use the H-index to
classify among A1, A2, B1, B2, B3, B4, B5. In Italy: C. H index = 20 . Average citation: 3.87. According to GII-GRIN-SCIE conference
rating.
The
acceptance rate should be advertised on the web site.
In
USA, what matters is if a competing conference has a close deadline.
Status of VLSI-SoC 2019
October
6-9, 2019, Cuzco, Peru
International
flights come to Lima and it takes around one hour from Lima to Cuzco by plain
Discussion and decision on VLSI-SOC 2021
Proposal
for VLSI-SOC 2021by Luciano Ost & Leandro Indrusiak (as for the details, see
slides)
York
is 200 miles north of London.
VLSI-SoC
will be the 40 years anniversary of conference creation.
As
for lodging:
University
of York: accommodation is cheap, but should be no later than mid-Sept.
Principal
Hotel: accommodation is expensive, better location
Mariott
Hotel: 20 min by bus from the city center, middle cost accommodation.
Break-even
point: 50
Foreseen
attendance: 100-150
University
would provide assistance for the web site and money management
Proposal
for VLSI-SOC 2021: Anupam Chattopadhyay & Andrea Calimera (as for the
details, see slides)
Singapore
on Sept 27 to 29 or Oct 4 to 6.
NTU
university, which is located in the north of the city.
Local
participation expected. There was a local workshop with 100 attendees.
Proposal
for VLSI-SOC 2021: Virendra Singh (as
for the details, see slides)
Indian
Institute of Technology, Mumbai, India
Explained
through video conference.
There are concerns on the lodging which may be a
little far from the conference center
Vote for
VLSI-SoC 2021
Singapore:
9
York:
3
Mumbai:
0
So, Singapore proposal has been granted
Conference
location for 2022
York
proposal is supposed to be improved following the guidelines
Next meeting: Firenze, March 2019, in conjunction with
DATE 2019